DM3730CUSD100
- 制造商编号：
- 品牌：
- 库存数量：
- 800件
- 售价：
- ¥160.000
- 上架时间：
- 2019/4/23 19:41:33
| 数量 | 价格 |
| 5+ | ¥160.000 |
| 50+ | ¥156.800 |
| 500+ | ¥156.800 |
| 1000+ | ¥156.800 |
| 3000+ | ¥156.800 |
The DM37x generation of high-performance, applications processors are based on the enhanced device architecture and are integrated on TI's advanced 45-nm process technology. This architecture is designed to provide best in class ARM and Graphics performance while delivering low power consumption. This balance of performance and power allow the device to support the following example applications:
Portable Data Terminals
Navigation
Auto Infotainment
Gaming
Medical Imaging
Home Automation
Human Interface
Industrial Control
Test and Measurement
Single board Computers
The device can support numerous HLOS and RTOS solutions including Linux and Windows Embedded CE which are available directly from TI. Additionally, the device is fully backward compatible with previous Cortex™-A8 processors and OMAP™ processors.
This DM3730/25 Digital Media Processor data manual presents the electrical and mechanical specifications for the DM3730/25 Applications Processor. The information contained in this data manual applies to both the commercial and extended temperature versions of the DM3730/25 Digital Media Processor unless otherwise indicated. It consists of the following sections:
A description of the DM3730/25 terminals: assignment, electrical characteristics, multiplexing, and functional description
A presentation of the electrical characteristics requirements: power domains, operating conditions, power consumption, and dc characteristics
The clock specifications: input and output clocks, DPLL and DLL
A description of thermal characteristics, device nomenclature, and mechanical data about the available packaging
特性
DM3730, DM3725 Digital Media Processors:
Eight Highly Independent Functional Units
Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle
Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-bit Multiplies (16-Bit Results) per Clock Cycle
Load-Store Architecture With Non-Aligned Support
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Additional C64x+™ Enhancements
Protected Mode Operation
Expectations Support for Error Detection and Program Redirection
Hardware Support for Modulo Loop Operation
Tile Based Acrchitecture Delivering up to 20 MPoly/sec
Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
Fine Grained Task Switching, Load Balancing, and Power Management
Programmable High Quality Image Anti-Aliasing
Up to 800-MHz TMS320C64x+™ DSP Core
Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
Video Hardware Accelerators
Up to 1-GHz ARM® Cortex™-A8 Core, Also supports 300, 600, and 800-MHz
NEON SIMD Coprocessor
Compatible with OMAP™ 3 Architecture
ARM® microprocessor (MPU) Subsystem
High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem
POWER SGX™ Graphics Accelerator (DM3730 only)
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
C64x+TM L1/L2 Memory Architecture
